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september 2006 rev 8 1/33 1 m24c16, m24c08 m24c04, m24c02, m24c01 16kbit, 8kbit, 4kbit, 2kbit an d 1kbit serial i2c bus eeprom feature summary two-wire i2c serial interface supports 400khz protocol single supply voltage: ? 2.5 to 5.5v for m24cxx-w ? 1.8 to 5.5v for m24cxx-r write control input byte and page write (up to 16 bytes) random and sequential read modes self-timed programming cycle automatic address incrementing enhanced esd/latch-up protection more than 1 million write cycles more than 40-year data retention packages ? ecopack? (rohs compliant) table 1. product list reference part number m24c16 m24c16-w m24c16-r m24c08 M24C08-W m24c08-r m24c04 m24c04-w m24c04-r m24c02 m24c02-w m24c02-r m24c01 m24c01-w m24c01-r pdip8 (bn) so8 (mn) 150 mil width tssop8 (dw) 169 mil width tssop8 (ds) 3x3mm2 body size ufdfpn8 (mb) 2x3mm2 (mlp) www.st.com
contents m24c16, m24c08, m24c04, m24c02, m24c01 2/33 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 chip enable (e0, e1, e2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3.1 write control (wc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4.2 power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4.3 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6.3 minimizing system delays by polling on ack . . . . . . . . . . . . . . . . . . . . . 15 3.7 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7.1 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7.2 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7.4 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
m24c16, m24c08, m24c04, m24c02, m24c01 contents 3/33 7 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
list of tables m24c16, m24c08, m24c04, m24c02, m24c01 4/33 list of tables table 1. product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. operating conditions (m24cxx-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 table 7. operating conditions (m24cxx-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 table 8. dc characteristics (m24cxx-w, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. dc characteristics (m24cxx-w, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. dc characteristics (m24cxx-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 13. ac characteristics (m24cxx-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14. ac characteristics (m24cxx-r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 15. pdip8 ? 8 pin plastic dip, 0.25mm lead fram e, package mechanical data . . . . . . . . . . . . 25 table 16. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 17. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2x3mm2, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18. tssop8 ? 8 lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . 28 table 19. tssop8 3x3mm2 ? 8 lead thin shrink small outline, 3x3mm2 body size, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 20. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 21. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
m24c16, m24c08, m24c04, m24c02, m24c01 list of figures 5/33 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. maximum r p value versus bus parasitic capacitance (c) for an i2c bus . . . . . . . . . . . . . . 9 figure 5. i2c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. write mode sequences with wc = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. write mode sequences with wc = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 figure 9. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package outline . . . . . . . . . . . . . . . . . . . . 25 figure 13. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline . . . . . . 26 figure 14. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2x3mm2, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 15. tssop8 ? 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . 28 figure 16. tssop8 3x3mm2 ? 8 lead thin shrink small outline, 3x3mm2 body size, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
summary description m24c16, m24c08, m24c04, m24c02, m24c01 6/33 1 summary description these i2c-compatible electric ally erasable programmable memory (eeprom) devices are organized as 2048/1024/512/256/128 x 8 (m24c16, m24c08, m24c04, m24c02 and m24c01). in order to meet environmental requirements, st offers these devices in ecopack? packages. ecopack? packages are lead-free and rohs compliant. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 1. logic diagram i2c uses a two-wire serial interface, comprising a bi-directional data line and a clock line. the devices carry a built-in 4-bit device type identifier code (1010) in accordance with the i2c bus definition. the device behaves as a slave in the i2c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and read/write bit (rw ) (as described in ta bl e 3 ), terminated by an acknowledge bit. when writing data to the memory, the device inserts an acknowledge bit during the 9 th bit time, following the bus master?s 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. table 2. signal names e0, e1, e2 chip enable sda serial data scl serial clock wc write control v cc supply voltage v ss ground ai02033 3 e0-e2 sda v cc m24cxx wc scl v ss
m24c16, m24c08, m24c04, m24c02, m24c01 summary description 7/33 figure 2. 8-pin package connections (top view) 1. nc = not connected 2. see section 7: package mechanical for package dimensions, and how to identify pin-1. sda v ss scl wc v cc / e2 ai02034e m24cxx 1 2 3 4 8 7 6 5 / e2 / e2 / e2 nc / e1 / e1 / e1 / nc nc / e0 / e0 / nc / nc nc /1kb /2kb /4kb /8kb 16kb
signal description m24c16, m24c08, m24c04, m24c02, m24c01 8/33 2 signal description 2.1 serial clock (scl) this input signal is used to strobe all data in and out of the device. in applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from serial clock (scl) to v cc . ( figure 4 indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of sy nchronization is not employed, and so the pull- up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 serial data (sda) this bi-directional signal is used to transfer data in or out of the device. it is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull up resistor must be connected from serial data (sda) to v cc . ( figure 4 indicates how the value of the pull-up resistor can be calculated). 2.3 chip enable (e0, e1, e2) these input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. these inputs must be tied to v cc or v ss , to establish the device select code as shown in figure 3 . figure 3. device select code 2.3.1 write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write operations are disabled to the entire memory array when write control (wc ) is driven high. when unconnected, the signal is internally read as v il , and write operations are allowed. when write control (wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. ai11650 v cc m24cxx v ss e i v cc m24cxx v ss e i
m24c16, m24c08, m24c04, m24c02, m24c01 signal description 9/33 2.4 supply voltage (v cc ) 2.4.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see ta bl e 6 and ta b l e 7 ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10nf to 100nf) close to the v cc /v ss package pins. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). the v cc rise time must not vary faster than 1v/s 2.4.2 power-up and device reset in order to prevent inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up (continuous rise of v cc ), the device does not respond to any instruction until v cc has reached the power on reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in ta bl e 6 and ta b l e 7 ). when v cc has passed the por threshold, the device is reset and in standby power mode. 2.4.3 power-down at power-down (where v cc decreases continuously), as soon as v cc drops from the operating voltage range to below the power on reset threshold voltage, the device stops responding to any inst ruction sent to it. during power-down, the device must be deselected and in the standby power mode (that is there should be no internal write cycle in progress). figure 4. maximum r p value versus bus parasitic capacitance (c) for an i2c bus ai01665b v cc c sda r p master r p scl c 100 0 4 8 12 16 20 c (pf) maximum rp value (k ? ) 10 1000 fc = 400khz fc = 100khz
signal description m24c16, m24c08, m24c04, m24c02, m24c01 10/33 figure 5. i2c bus protocol table 3. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable (2),(3) 2. e0, e1 and e2 are compared against the respec tive external pins on the memory device. 3. a10, a9 and a8 represent most significant bits of the address. rw b7 b6 b5 b4 b3 b2 b1 b0 m24c01 select code1010e2e1e0rw m24c02 select code1010e2e1e0rw m24c04 select code1010e2e1a8rw m24c08 select code1010e2a9a8rw m24c16 select code1010a10a9a8rw scl sda scl sda sda start condition sda input sda change ai00792b stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
m24c16, m24c08, m24c04, m24c02, m24c01 device operation 11/33 3 device operation the device supports the i2c protocol. this is summarized in figure 5 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a data transfer can on ly be initiated by the bus master, which will also provide the serial clock for synchronization. the m24cxx device is always a slave in all communication. 3.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer command. the device continuously monitors (except during a write cycle) serial data (sda) and serial clock (scl) for a start condition, and will not respond unless one is given. 3.2 stop condition stop is identified by a rising edge of serial data (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read command that is followed by noack can be followed by a stop condition to force the device into the stand-by mode. a stop condition at the end of a write command triggers the internal write cycle. 3.3 acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter, whether it be bus master or slave device, releases serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. 3.4 data input during data input, the device samples serial data (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low.
device operation m24c16, m24c08, m24c04, m24c02, m24c01 12/33 3.5 memory addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. following this, t he bus master sends the device select code, shown in ta b l e 3 (on serial data (sda), most significant bit first). the device select code consists of a 4-bit de vice type identifier, and a 3-bit chip enable ?address? (e2, e1, e0). to address the memory array, the 4-bit device type identifier is 1010b. each device is given a unique 3-bit code on the chip enable (e0, e1, e2) inputs. when the device select code is received, the device only responds if the chip enable address is the same as the value on the chip enable (e0, e1, e2) inputs. however, those devices with larger memory capacities (the m24c16, m24c08 and m24c04) need more address bits. e0 is not available for use on devices that need to use address line a8; e1 is not available for devices that need to use address line a9, and e2 is not available for devices that need to use address line a10 (see figure 2 and ta b l e 3 for details). using the e0, e1 and e2 inputs, up to eight m24c02 (or m24c01), four m24c04, two m24c08 or one m24c16 devices can be connected to one i2c bus. in each case, and in the hybrid cases, this gives a total memory capacity of 16 kbits, 2 kbytes (except where m24c01 devices are used). the 8 th bit is the read/write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, it deselects itself from the bus, and goes into stand-by mode. table 4. operating modes mode rw bit wc (1) 1. x = v ih or v il . bytes initial sequence current address read 1 x 1 s tart, device select, rw = 1 random address read 0x 1 start, device select, rw = 0, address 1 x restart, device select, rw = 1 sequential read 1 x 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il 16 start, device select, rw = 0
m24c16, m24c08, m24c04, m24c02, m24c01 device operation 13/33 figure 6. write mode sequences with wc = 1 (data write inhibited) 3.6 write operations following a start condition the bus master sends a device select code with the read/write bit (rw ) reset to 0. the device acknowledges this, as shown in figure 7 , and waits for an address byte. the device responds to the address byte with an acknowledge bit, and then waits for the data byte. when the bus master generates a stop condition immediately after the ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. during the internal write cycle, serial data (sda) and serial clock (scl) are ignored, and the device does not respond to any requests. 3.6.1 byte write after the device select code and the address byte, the bus master sends one data byte. if the addressed location is write-protected, by write control (wc ) being driven high (during the period from the start condition until the end of the address byte), the device replies to the data byte with noack, as shown in figure 6 , and the location is not modified. if, instead, the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 7 . stop start byte write dev sel byte addr data in wc start page write dev sel byte addr data in 1 data in 2 wc data in 3 ai02803c page write (cont'd) wc (cont'd) stop data in n ack ack no ack r/w ack ack no ack no ack r/w no ack no ack
device operation m24c16, m24c08, m24c04, m24c02, m24c01 14/33 3.6.2 page write the page write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. if more byte s are sent than will fit up to the end of the page, a condition known as ?roll-over? occurs. this should be avoided, as data starts to become overwritten in an implementation dependent way. the bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if write control (wc ) is low. if the addressed location is write-protected, by write control (wc ) being driven high (during the period from the start condition until the end of the address byte), the device replies to the data bytes with noack, as shown in figure 6 , and the locations are not modified. after each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. the transfer is terminated by the bus master generating a stop condition. figure 7. write mode sequences with wc = 0 (data write enabled) stop start byte write dev sel byte addr data in wc start page write dev sel byte addr data in 1 data in 2 wc data in 3 ai02804b page write (cont'd) wc (cont'd) stop data in n ack r/w ack ack ack ack ack ack r/w ack ack
m24c16, m24c08, m24c04, m24c02, m24c01 device operation 15/33 figure 8. write cycle polling flowchart using ack 3.6.3 minimizing system delays by polling on ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in ta bl e 1 3 and ta bl e 1 4 , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 8 , is: initial condition: a writ e cycle is in progress. step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). step 2: if the device is busy with the inte rnal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). write cycle in progress ai01847c next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation
device operation m24c16, m24c08, m24c04, m24c02, m24c01 16/33 figure 9. read mode sequences 1. the seven most significant bits of the device select code of a random read (in the 1 st and 3 rd bytes) must be identical. 3.7 read operations read operations are performed independently of the state of the write control (wc ) signal. the device has an internal address counter which is incremented each time a byte is read. 3.7.1 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 9 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. start dev sel * byte addr start dev sel data out 1 ai01942 data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack r/w ack ack ack no ack r/w no ack ack ack r/w ack ack r/w ack no ack
m24c16, m24c08, m24c04, m24c02, m24c01 device operation 17/33 3.7.2 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 9 , without acknowledging the byte. 3.7.3 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 9 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 3.7.4 acknowledg e in read mode for all read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during this time, the device terminates the data transfer and switches to its stand-by mode.
initial delivery state m24c16, m24c08, m24c04, m24c02, m24c01 18/33 4 initial delivery state the device is delivered with all bits in the memory array set to 1 (each byte contains ffh). 5 maximum rating stressing the device outside the ratings listed in ta bl e 5 may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroe lectronics sure program and other relevant quality documents. 1. t lead max must not be applied for more than 10s. 2. aec-q100-002 (compliant wi th jedec std jesd22-a114a, c1=100pf, r1=1500 ? , r2=500 ? ). table 5. absolute maximum ratings symbol parameter min. max. unit t a ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std- 020c (for small body, sn-pb or pb assembly), the st ecopack? 7191395 specification, and the european directive on re strictions on hazardous substances (rohs) 2002/95/eu. c pdip-specific lead temperature during soldering 260 (2) 2. t lead max must not be applied for more than 10s. c v io input or output range ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) (2) ?4000 4000 v
m24c16, m24c08, m24c04, m24c02, m24c01 dc and ac parameters 19/33 6 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 6. operating conditions (m24cxx-w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 c table 7. operating conditions (m24cxx-r) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 8. dc characteristics (m24cxx-w, device grade 6) symbol parameter test condition (in addition to those in table 6 ) min. max. unit i li input leakage current (scl, sda, e0, e1,and e2) v in = v ss or v cc , device in standby mode 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current v cc =5v, f c =400khz (rise/fall time < 30ns) 2ma v cc =2.5v, f c =400khz (rise/fall time < 30ns) 1ma i cc1 stand-by supply current v in = v ss or v cc , for 2.5v < v cc = < 5.5v 1a v il input low voltage (1) 1. the voltage source driv ing only e0, e1 and e2 inputs must provide an impedance of less than 1k ? . ?0.45 0.3v cc v v ih input high voltage (1) 0.7v cc v cc +1 v v ol output low voltage i ol = 2.1ma when v cc = 2.5v or i ol = 3ma when v cc = 5.5v 0.4 v
dc and ac parameters m24c16, m24c08, m24c04, m24c02, m24c01 20/33 table 9. dc characteristics (m24cxx-w, device grade 3) symbol parameter test condition (in addition to those in table 6 ) min. max. unit i li input leakage current (scl, sda, e0, e1,and e2) v in = v ss or v cc , device in standby mode 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current v cc =5v, f c =400khz (rise/fall time < 30ns) 3ma v cc =2.5v, f c =400khz (rise/fall time < 30ns) 3ma i cc1 stand-by supply current v in = v ss or v cc , v cc = 5 v 5 a v in = v ss or v cc , v cc = 2.5 v 2 a v il input low voltage (1) 1. the voltage source driv ing only e0, e1 and e2 inputs must provide an impedance of less than 1k ? . ?0.45 0.3v cc v v ih input high voltage (1) 0.7v cc v cc +1 v v ol output low voltage i ol = 2.1ma when v cc = 2.5v or i ol = 3ma when v cc = 5.5v 0.4 v table 10. dc characteristics (m24cxx-r) symbol parameter test condition (in addition to those in table 7 ) min. max. unit i li input leakage current (scl, sda, e0, e1,and e2) v in = v ss or v cc , device in standby mode 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current v cc =1.8v, f c =400khz (rise/fall time < 30ns) 0.8 ma i cc1 stand-by supply current v in = v ss or v cc , 1.8v < v cc < 2.5v 1a v il input low voltage (1) 1. the voltage source driv ing only e0, e1 and e2 inputs must provide an impedance of less than 1k ? . 2.5 v v cc ?0.45 0.3 v cc v 1.8 v v cc < 2.5v ?0.45 0.25v cc v v ih input high voltage (1) 0.7v cc v cc +1 v v ol output low voltage i ol = 0.7 ma, v cc = 1.8 v 0.2 v
m24c16, m24c08, m24c04, m24c02, m24c01 dc and ac parameters 21/33 figure 10. ac measurement i/o waveform table 11. ac measurement conditions symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input levels 0.2v cc to 0.8v cc v input and output timi ng reference levels 0.3v cc to 0.7v cc v table 12. input parameters symbol parameter (1),(2) 1. t a = 25c, f = 400khz 2. sampled only, not 100% tested. test condition min. max. unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z wcl wc input impedance v in < 0.3 v 15 70 k ? z wch wc input impedance v in > 0.7v cc 500 k ? t ns pulse width ignored (input filter on scl and sda) single glitch 100 ns ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
dc and ac parameters m24c16, m24c08, m24c04, m24c02, m24c01 22/33 table 13. ac characteristics (m24cxx-w) test conditions specified in table 6 and table 11 symbol alt. parameter min. max. unit f c f scl clock frequency 400 khz t chcl t high clock pulse width high 600 ns t clch t low clock pulse width low 1300 ns t dl1dl2 (1) 1. sampled only, not 100% tested. t f sda fall time 20 300 ns t dxcx t su:dat data in set up time 100 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 200 ns t clqv (2) 2. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. t aa clock low to next data valid (access time) 200 900 ns t chdx (3) 3. for a restart condition, or following a write cycle. t su:sta start condition set up time 600 ns t dlcl t hd:sta start condition hold time 600 ns t chdh t su:sto stop condition set up time 600 ns t dhdl t buf time between stop condition and next start condition 1300 ns t w (4) 4. previous devices bearing the proces s letter ?l? in the package marking guarantee a maximum write time of 10ms. for more information about these devices and thei r device identification, pl ease ask your st sales office for process change notices pcn mpg/ee/0061 and 0062 (pcee0061 and pcee0062). t wr write time 5 ms
m24c16, m24c08, m24c04, m24c02, m24c01 dc and ac parameters 23/33 table 14. ac characteristics (m24cxx-r) test conditions specified in table 7 and table 10 symbol alt. parameter min. max. unit f c f scl clock frequency 400 khz t chcl t high clock pulse width high 600 ns t clch t low clock pulse width low 1300 ns t dl1dl2 (1) 1. sampled only, not 100% tested. t f sda fall time 20 300 ns t dxcx t su:dat data in set up time 100 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 200 ns t clqv (2) 2. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. t aa clock low to next data valid (access time) 200 900 ns t chdx (3) 3. for a restart condition, or following a write cycle. t su:sta start condition set up time 600 ns t dlcl t hd:sta start condition hold time 600 ns t chdh t su:sto stop condition set up time 600 ns t dhdl t buf time between stop condition and next start condition 1300 ns t w t wr write time 10 ms
dc and ac parameters m24c16, m24c08, m24c04, m24c02, m24c01 24/33 figure 11. ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop condition data valid tclqv tclqx tchdh stop condition tchdx start condition write cycle tw ai00795c start condition
m24c16, m24c08, m24c04, m24c02, m24c01 package mechanical 25/33 7 package mechanical figure 12. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package outline 1. drawing is not to scale. table 15. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package mechanical data symbol millimeters inches typ. min. max. typ. min. max. a 5.33 0.210 a1 0.38 0.015 a2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 d 9.27 9.02 10.16 0.365 0.355 0.400 e 7.87 7.62 8.26 0.310 0.300 0.325 e1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 ? ? 0.100 ? ? ea 7.62 ? ? 0.300 ? ? eb 10.92 0.430 l 3.30 2.92 3.81 0.130 0.115 0.150 pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e
package mechanical m24c16, m24c08, m24c04, m24c02, m24c01 26/33 figure 13. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline 1. drawing is not to scale. 2. the ?1? that appears in the top view of the package show s the position of pin 1 and the ?n? indicates the total number of pins. table 16. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a1.750.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e1.27? ?0.050? ? h 0.25 0.50 0.010 0.020 k0808 l 0.40 1.27 0.016 0.050 l1 1.04 0.041 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
m24c16, m24c08, m24c04, m24c02, m24c01 package mechanical 27/33 figure 14. ufdfpn8 (mlp8) 8-lead ultra th in fine pitch dual flat package no lead 2x3mm2, outline 1. drawing is not to scale. 2. the central pad (the area e2 by d2 in the abov e illustration) is pulle d, internally, to v ss . it must not be allowed to be connected to any other voltage or sig nal line on the pcb, for example during the soldering process. 3. the circle in the top view of the package indicates the position of pin 1. table 17. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2x3mm2, data symbol millimeters inches typ min max typ min max a 0.55 0.50 0.60 0.022 0.020 0.024 a1 0.02 0.00 0.05 0.001 0.000 0.002 b 0.25 0.20 0.30 0.010 0.008 0.012 d 2.00 1.90 2.10 0.079 0.075 0.083 d2 1.60 1.50 1.70 0.063 0.059 0.067 ddd 0.08 0.003 e 3.00 2.90 3.10 0.118 0.114 0.122 e2 0.20 0.10 0.30 0.008 0.004 0.012 e0.50? ?0.020? ? l 0.45 0.40 0.50 0.018 0.016 0.020 l1 0.15 0.006 l3 0.30 0.012 d e ufdfpn-01 a a1 ddd l1 e b d2 l e2 l3
package mechanical m24c16, m24c08, m24c04, m24c02, m24c01 28/33 figure 15. tssop8 ? 8 lead thin shrink small outline, package outline 1. drawing is not to scale. 2. the circle in the top view of the package indicates the position of pin 1. table 18. tssop8 ? 8 lead thin shrink small outline, package mechanical data symbol millimeters inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
m24c16, m24c08, m24c04, m24c02, m24c01 package mechanical 29/33 figure 16. tssop8 3x3mm2 ? 8 lead thin shrink small outline, 3x3mm2 body size, package outline 1. drawing is not to scale. 2. the circle in the top view of the package indicates the position of pin 1. table 19. tssop8 3x3mm2 ? 8 lead thin shrink small outline, 3x3mm2 body size, mechanical data symbol millimeters inches typ. min. max. typ. min. max. a 1.100 0.0433 a1 0.050 0.150 0.0020 0.0059 a2 0.850 0.750 0.950 0.0335 0.0295 0.0374 b 0.250 0.400 0.0098 0.0157 c 0.130 0.230 0.0051 0.0091 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 4.900 4.650 5.150 0.1929 0.1831 0.2028 e1 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? cp 0.100 0.0039 l 0.550 0.400 0.700 0.0217 0.0157 0.0276 l1 0.950 0.0374 0 6 0 6 tssop8bm 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
part numbering m24c16, m24c08, m24c04, m24c02, m24c01 30/33 8 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. table 20. ordering information scheme example: m24c16 ? w dw 3 t p /w device type m24 = i 2 c serial access eeprom device function 16 = 16 kbit (2048 x 8) 08 = 8 kbit (1024 x 8) 04 = 4 kbit (512 x 8) 02 = 2 kbit (256 x 8) 01 = 1 kbit (128 x 8) operating voltage w = v cc = 2.5 to 5.5v (400 khz) r = v cc = 1.8 to 5.5v (400 khz) package bn = pdip8 mn = so8 (150 mil width) mb = udfdfpn8 (mlp8) dw = tssop8 (169 mil width) ds = tssop8 (3x3mm2 body size, msop8) (1) 1. products sold in this package are not recommended for new design. device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow 3 = device tested with high reliability certified flow (2) . automotive temperature range (?40 to 125 c) 2. st strongly recommends the use of the automo tive grade devices fo r use in an automotive environment. the high reliability certified flow (hrcf) is described in the quality note qnee9801. please ask your nearest st sales office for a copy. option t = tape and reel packing plating technology blank = standard snpb plating p or g = ecopack? (rohs compliant) process (3) 3. used only for device grade 3. /w or /s = f6sp36%
m24c16, m24c08, m24c04, m24c02, m24c01 revision history 31/33 9 revision history table 21. document revision history date version changes 10-dec-1999 2.4 tssop8 turned-die package removed (p 2 and order information) lead temperature added for tssop8 in table 2 18-apr-2000 2.5 labelling change to fig-2d, correction of values for ?e? and main caption for tab-13 05-may-2000 2.6 extra labelling to fig-2d 23-nov-2000 3.0 sbga package information removed to an annex document -r range changed to being the -s range, and the new -r range added 19-feb-2001 3.1 sbga package information put back in this document lead soldering temperature in the absolute maximum ratings table amended write cycle polling flow chart using ack illustration updated references to psdip changed to pdip and package mechanical data updated wording brought in to line with standard glossary 20-apr-2001 3.2 revision of dc and ac characteristics for the -s series 08-oct-2001 3.3 ball numbers added to the sbga connections and package mechanical illustrations 09-nov-2001 3.4 specification of test condition for leakage currents in the dc characteristics table improved 30-jul-2002 3.5 document reformatted using new template. sbga5 package removed tssop8 (3x3mm2 body size) package (msop8) added. -l voltage range added 04-feb-2003 3.6 document title spelt out more full y. ?w?-marked devices with tw=5ms added. 05-may-2003 3.7 -r voltage range upgraded to 400khz working, and no longer preliminary data. 5v voltage range at temperature range 3 (-xx3) no longer preliminary data. -s voltage range removed. -wxx3 voltage+temp ranged added as preliminary data. 07-oct-2003 4.0 table of contents, and pb-free options added. minor wording changes in summary description, power-on re set, memory addressing, read operations. v il (min) improved to -0.45v. t w (max) value for -r voltage range corrected. 17-mar-2004 5.0 mlp package added. absolute maximum ratings for v io (min) and v cc (min) changed. soldering temperature information clarified for rohs compliant devices. device grade information clarified. process identification letter ?g? information added. 2.2-5.5v range is removed, and 4.5-5.5v range is now not for new design
revision history m24c16, m24c08, m24c04, m24c02, m24c01 32/33 7-oct-2005 6.0 product list summary table added. aec-q100-002 compliance. device grade information clarified. updated device internal reset section, figure 3 , figure 4 , ta b l e 1 4 and ta b l e 2 0 added ecopack? information. updated tw=5ms for the m24cxx-w. 17-jan-2006 7.0 pin numbers removed from silhouettes (see on page 1 ). internal device reset paragraph moved to below section 2.4: supply voltage (vcc) . section 2.4: supply voltage (vcc) added below section 2: signal description . test conditions for v ol updated in ta bl e 8 and ta b l e 9 so8n package specifications updated (see ta bl e 1 6 ) new definition of i cc1 over the whole v cc range (see tables 8 , 9 and 10 ). 19-sep-2006 8 document converted to new st template. so8 and ufdfpn8 package spec ifications updated (see section 7: package mechanical ). section 2.4: supply voltage (vcc) clarified. i li value given with the device in standby mode in tables 8 , 9 and 10 . information given in table 14: ac characteristics (m24cxx-r) are no longer preliminary data. table 21. document revision history date version changes
m24c16, m24c08, m24c04, m24c02, m24c01 33/33 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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